The present invention relates to a semiconductor memory device, and more particularly to an input circuit of a semiconductor memory device which inputs data into an internal circuit during a write operation.
In general, a data input buffer is turned on to buffer data when a write command is inputted, and turned off after ensuring a burst operation.
Typically, an externally input write command is decoded and then latched in synchronization with an internal clock, and is thereby converted into a write pulse. The data input buffer is turned on when the write pulse is generated.
In other words, a typical data input buffer is turned on by a write pulse generated in synchronization with an internal clock so that the data input buffer can buffer data.
A typical write pulse generation circuit for generating a write pulse is configured as shown in FIG. 1.
Specifically, referring to FIG. 1, the typical write pulse generation circuit receives, via the gates of NMOS transistors N2 and N3, an input signal IN generated by decoding a write command and an inverted input signal INB whose phase is the inverse of the input signal IN, respectively. Hereinafter, the input signal IN is assumed to be of a high level.
An internal clock ICLK is toggled and a NMOS transistor N1 is turned on when the internal clock ICLK becomes a high level. PMOS transistors P1 and P2 and NMOS transistors N4 and N5 (which are configured in a latch structure) allow node ND1 to maintain a low level and node ND2 to maintain a high level.
An inverter INVL inverts the signal of the node ND1 to output a write pulse WTP. The signal of the node ND2 is inputted into an inverter INV2; however, this signal is unnecessary and thus the output terminal of the inverter INV2 is floated.
Thereafter, when the internal clock ICLK transitions to the low level, PMOS transistors P3 to P5 are turned on to precharge the two nodes ND1 and ND2 to the high level.
As such, the write pulse WTP is synchronized with the internal clock ICLK and is enabled when the internal clock ICLK is enabled (the high level) and disabled when the internal clock ICLK is disabled (the low level).
However, in conditions in which the additive latency (AL) is ‘0’ and column access strobe (CAS) latency (CL) is ‘2’ in DDR1 or DDR2, data is inputted after ‘1[tck]’ (i.e., one period of the clock) after the input of the write command. At this time, the data may be inputted at ‘1[tck]-0.25[tck]’ under a condition in which tDQSS (the time from the clock to the first rising edge of the data strobe signal DQS-In) is minimum.
In this case, no problems occur during low frequency operation; however, during high frequency operation, the enabling point of the write pulse WTP can be delayed when variations in external environment (for example; process, voltage, and temperature) occur.
Accordingly, during high frequency operation, data is input into the data input buffer before the data input buffer is turned on, since the data is inputted into the data input buffer without delay, while the write pulse WTP is enabled late. Therefore, there is a problem in the typical configuration, in that defects are generated when data is not buffered normally.